<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<center><big><big><b>System Settings</b></big></big></center><br>
<A NAME="Environment Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Environment Variable</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
</tr>
<tr>
<td>Path</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\\lib\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\lib\nt64;<br>C:\software\electronica\xilinx\Vivado\2012.1\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\PlanAhead\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\lib\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnuwin\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnu\arm\nt64\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\common\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\common\lib\nt64;<br>c:\windows\system32;<br>c:\windows;<br>c:\windows\system32\wbem;<br>c:\windows\system32\windowspowershell\v1.0\;<br>c:\Python27\Lib\site-packages\PyQt4;<br>c:\software\programacion\CollabNet\SVNClient;<br>C:\software\utilidades\LyX\MiKTeX-2.9\miktex\bin;<br>C:\software\utilidades\LyX20\MiKTeX 2.9\miktex\bin;<br>C:\software\bbdd\oracle\Ora11gr2_x64\cliente\bin;<br>c:\software\PROGRA~1\CBUILD~1\Bin;<br>c:\jdk\jdk1.6.0_24-32bits\javafx-sdk1.3\bin;<br>c:\jdk\jdk1.6.0_24-32bits\javafx-sdk1.3\emulator\bin;<br>c:\software\utilidades\LEd\MiKTeX 2.9\miktex\bin;<br>C:\Program Files\Intel\DMIX;<br>C:\Program Files (x86)\Pico Technology\PicoScope6\;<br>C:\software\MATLABr2010b\runtime\win64;<br>C:\software\MATLABr2010b\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\pcb\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\fet\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\specctra\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\PSpice;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\PSpice\Library;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\Capture;<br>C:\software\electronica\OrCAD\OrCAD_15.7\OpenAccess\bin\win32\opt;<br>C:\software\programacion\Protege_3.4.8\Graphviz\bin;<br>C:\Python27;<br>C:\Python27\DLLs;<br>C:\Python27\Scripts;<br>c:\Python27\Lib\site-packages\vtk;<br>c:\Python27\gnuplot\binary;<br>c:\software\programacion\pythonxy\SciTE-3.1.0;<br>c:\software\programacion\pythonxy\console;<br>C:\MinGW32-xy\bin;<br>c:\software\programacion\pythonxy\swig;<br>c:\software\programacion\pythonxy\gettext\bin;<br>C:\software\electronica\modelsim\win64;<br>C:\Program Files\Microsoft\Web Platform Installer\;<br>C:\Program Files (x86)\Microsoft ASP.NET\ASP.NET Web Pages\v1.0\;<br>C:\Program Files (x86)\Windows Kits\8.0\Windows Performance Toolkit\;<br>C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;<br>C:\software\programacion\TortoiseSVN\bin</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\\lib\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\lib\nt64;<br>C:\software\electronica\xilinx\Vivado\2012.1\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\PlanAhead\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\lib\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnuwin\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnu\arm\nt64\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\common\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\common\lib\nt64;<br>c:\windows\system32;<br>c:\windows;<br>c:\windows\system32\wbem;<br>c:\windows\system32\windowspowershell\v1.0\;<br>c:\Python27\Lib\site-packages\PyQt4;<br>c:\software\programacion\CollabNet\SVNClient;<br>C:\software\utilidades\LyX\MiKTeX-2.9\miktex\bin;<br>C:\software\utilidades\LyX20\MiKTeX 2.9\miktex\bin;<br>C:\software\bbdd\oracle\Ora11gr2_x64\cliente\bin;<br>c:\software\PROGRA~1\CBUILD~1\Bin;<br>c:\jdk\jdk1.6.0_24-32bits\javafx-sdk1.3\bin;<br>c:\jdk\jdk1.6.0_24-32bits\javafx-sdk1.3\emulator\bin;<br>c:\software\utilidades\LEd\MiKTeX 2.9\miktex\bin;<br>C:\Program Files\Intel\DMIX;<br>C:\Program Files (x86)\Pico Technology\PicoScope6\;<br>C:\software\MATLABr2010b\runtime\win64;<br>C:\software\MATLABr2010b\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\pcb\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\fet\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\specctra\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\PSpice;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\PSpice\Library;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\Capture;<br>C:\software\electronica\OrCAD\OrCAD_15.7\OpenAccess\bin\win32\opt;<br>C:\software\programacion\Protege_3.4.8\Graphviz\bin;<br>C:\Python27;<br>C:\Python27\DLLs;<br>C:\Python27\Scripts;<br>c:\Python27\Lib\site-packages\vtk;<br>c:\Python27\gnuplot\binary;<br>c:\software\programacion\pythonxy\SciTE-3.1.0;<br>c:\software\programacion\pythonxy\console;<br>C:\MinGW32-xy\bin;<br>c:\software\programacion\pythonxy\swig;<br>c:\software\programacion\pythonxy\gettext\bin;<br>C:\software\electronica\modelsim\win64;<br>C:\Program Files\Microsoft\Web Platform Installer\;<br>C:\Program Files (x86)\Microsoft ASP.NET\ASP.NET Web Pages\v1.0\;<br>C:\Program Files (x86)\Windows Kits\8.0\Windows Performance Toolkit\;<br>C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;<br>C:\software\programacion\TortoiseSVN\bin</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\\lib\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\lib\nt64;<br>C:\software\electronica\xilinx\Vivado\2012.1\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\PlanAhead\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\lib\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnuwin\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnu\arm\nt64\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\common\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\common\lib\nt64;<br>c:\windows\system32;<br>c:\windows;<br>c:\windows\system32\wbem;<br>c:\windows\system32\windowspowershell\v1.0\;<br>c:\Python27\Lib\site-packages\PyQt4;<br>c:\software\programacion\CollabNet\SVNClient;<br>C:\software\utilidades\LyX\MiKTeX-2.9\miktex\bin;<br>C:\software\utilidades\LyX20\MiKTeX 2.9\miktex\bin;<br>C:\software\bbdd\oracle\Ora11gr2_x64\cliente\bin;<br>c:\software\PROGRA~1\CBUILD~1\Bin;<br>c:\jdk\jdk1.6.0_24-32bits\javafx-sdk1.3\bin;<br>c:\jdk\jdk1.6.0_24-32bits\javafx-sdk1.3\emulator\bin;<br>c:\software\utilidades\LEd\MiKTeX 2.9\miktex\bin;<br>C:\Program Files\Intel\DMIX;<br>C:\Program Files (x86)\Pico Technology\PicoScope6\;<br>C:\software\MATLABr2010b\runtime\win64;<br>C:\software\MATLABr2010b\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\pcb\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\fet\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\specctra\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\PSpice;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\PSpice\Library;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\Capture;<br>C:\software\electronica\OrCAD\OrCAD_15.7\OpenAccess\bin\win32\opt;<br>C:\software\programacion\Protege_3.4.8\Graphviz\bin;<br>C:\Python27;<br>C:\Python27\DLLs;<br>C:\Python27\Scripts;<br>c:\Python27\Lib\site-packages\vtk;<br>c:\Python27\gnuplot\binary;<br>c:\software\programacion\pythonxy\SciTE-3.1.0;<br>c:\software\programacion\pythonxy\console;<br>C:\MinGW32-xy\bin;<br>c:\software\programacion\pythonxy\swig;<br>c:\software\programacion\pythonxy\gettext\bin;<br>C:\software\electronica\modelsim\win64;<br>C:\Program Files\Microsoft\Web Platform Installer\;<br>C:\Program Files (x86)\Microsoft ASP.NET\ASP.NET Web Pages\v1.0\;<br>C:\Program Files (x86)\Windows Kits\8.0\Windows Performance Toolkit\;<br>C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;<br>C:\software\programacion\TortoiseSVN\bin</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\\lib\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\lib\nt64;<br>C:\software\electronica\xilinx\Vivado\2012.1\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\PlanAhead\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\lib\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnuwin\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\EDK\gnu\arm\nt64\bin;<br>C:\software\electronica\xilinx\14.1\ISE_DS\common\bin\nt64;<br>C:\software\electronica\xilinx\14.1\ISE_DS\common\lib\nt64;<br>c:\windows\system32;<br>c:\windows;<br>c:\windows\system32\wbem;<br>c:\windows\system32\windowspowershell\v1.0\;<br>c:\Python27\Lib\site-packages\PyQt4;<br>c:\software\programacion\CollabNet\SVNClient;<br>C:\software\utilidades\LyX\MiKTeX-2.9\miktex\bin;<br>C:\software\utilidades\LyX20\MiKTeX 2.9\miktex\bin;<br>C:\software\bbdd\oracle\Ora11gr2_x64\cliente\bin;<br>c:\software\PROGRA~1\CBUILD~1\Bin;<br>c:\jdk\jdk1.6.0_24-32bits\javafx-sdk1.3\bin;<br>c:\jdk\jdk1.6.0_24-32bits\javafx-sdk1.3\emulator\bin;<br>c:\software\utilidades\LEd\MiKTeX 2.9\miktex\bin;<br>C:\Program Files\Intel\DMIX;<br>C:\Program Files (x86)\Pico Technology\PicoScope6\;<br>C:\software\MATLABr2010b\runtime\win64;<br>C:\software\MATLABr2010b\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\pcb\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\fet\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\specctra\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\bin;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\PSpice;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\PSpice\Library;<br>C:\software\electronica\OrCAD\OrCAD_15.7\tools\Capture;<br>C:\software\electronica\OrCAD\OrCAD_15.7\OpenAccess\bin\win32\opt;<br>C:\software\programacion\Protege_3.4.8\Graphviz\bin;<br>C:\Python27;<br>C:\Python27\DLLs;<br>C:\Python27\Scripts;<br>c:\Python27\Lib\site-packages\vtk;<br>c:\Python27\gnuplot\binary;<br>c:\software\programacion\pythonxy\SciTE-3.1.0;<br>c:\software\programacion\pythonxy\console;<br>C:\MinGW32-xy\bin;<br>c:\software\programacion\pythonxy\swig;<br>c:\software\programacion\pythonxy\gettext\bin;<br>C:\software\electronica\modelsim\win64;<br>C:\Program Files\Microsoft\Web Platform Installer\;<br>C:\Program Files (x86)\Microsoft ASP.NET\ASP.NET Web Pages\v1.0\;<br>C:\Program Files (x86)\Windows Kits\8.0\Windows Performance Toolkit\;<br>C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;<br>C:\software\programacion\TortoiseSVN\bin</td>
</tr>
<tr>
<td>XILINX</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\ISE\</td>
</tr>
<tr>
<td>XILINXD_LICENSE_FILE</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\common\licenses\xilinx.lic</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\common\licenses\xilinx.lic</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\common\licenses\xilinx.lic</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\common\licenses\xilinx.lic</td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\ISE</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\ISE</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\ISE</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\ISE</td>
</tr>
<tr>
<td>XILINX_EDK</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\EDK</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\EDK</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\EDK</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\EDK</td>
</tr>
<tr>
<td>XILINX_PLANAHEAD</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\PlanAhead</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\PlanAhead</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\PlanAhead</td>
<td>C:\software\electronica\xilinx\14.1\ISE_DS\PlanAhead</td>
</tr>
<tr>
<td>XILINX_VIVADO</td>
<td>C:\software\electronica\xilinx\Vivado\2012.1</td>
<td>C:\software\electronica\xilinx\Vivado\2012.1</td>
<td>C:\software\electronica\xilinx\Vivado\2012.1</td>
<td>C:\software\electronica\xilinx\Vivado\2012.1</td>
</tr>
</TABLE>
<A NAME="Synthesis Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ifn</td>
<td>&nbsp;</td>
<td>conversor.prj</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ifmt</td>
<td>&nbsp;</td>
<td>mixed</td>
<td>MIXED</td>
</tr>
<tr>
<td>-ofn</td>
<td>&nbsp;</td>
<td>conversor</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofmt</td>
<td>&nbsp;</td>
<td>NGC</td>
<td>NGC</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc3s1000-5-ft256</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-top</td>
<td>&nbsp;</td>
<td>conversor</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-opt_mode</td>
<td>Optimization Goal</td>
<td>Speed</td>
<td>SPEED</td>
</tr>
<tr>
<td>-opt_level</td>
<td>Optimization Effort</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>-iuc</td>
<td>Use synthesis Constraints File</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-keep_hierarchy</td>
<td>Keep Hierarchy</td>
<td>No</td>
<td>NO</td>
</tr>
<tr>
<td>-netlist_hierarchy</td>
<td>Netlist Hierarchy</td>
<td>As_Optimized</td>
<td>as_optimized</td>
</tr>
<tr>
<td>-rtlview</td>
<td>Generate RTL Schematic</td>
<td>Yes</td>
<td>NO</td>
</tr>
<tr>
<td>-glob_opt</td>
<td>Global Optimization Goal</td>
<td>AllClockNets</td>
<td>ALLCLOCKNETS</td>
</tr>
<tr>
<td>-read_cores</td>
<td>Read Cores</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-write_timing_constraints</td>
<td>Write Timing Constraints</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-cross_clock_analysis</td>
<td>Cross Clock Analysis</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-bus_delimiter</td>
<td>Bus Delimiter</td>
<td>&lt;&gt;</td>
<td>&lt;&gt;</td>
</tr>
<tr>
<td>-slice_utilization_ratio</td>
<td>Slice Utilization Ratio</td>
<td>100</td>
<td>100%</td>
</tr>
<tr>
<td>-bram_utilization_ratio</td>
<td>BRAM Utilization Ratio</td>
<td>100</td>
<td>100%</td>
</tr>
<tr>
<td>-verilog2001</td>
<td>Verilog 2001</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-fsm_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-fsm_encoding</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-safe_implementation</td>
<td>&nbsp;</td>
<td>No</td>
<td>NO</td>
</tr>
<tr>
<td>-fsm_style</td>
<td>&nbsp;</td>
<td>LUT</td>
<td>LUT</td>
</tr>
<tr>
<td>-ram_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-ram_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-rom_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-shreg_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-rom_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-auto_bram_packing</td>
<td>&nbsp;</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-resource_sharing</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-async_to_sync</td>
<td>&nbsp;</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-mult_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-iobuf</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-max_fanout</td>
<td>&nbsp;</td>
<td>100000</td>
<td>500</td>
</tr>
<tr>
<td>-bufg</td>
<td>&nbsp;</td>
<td>8</td>
<td>8</td>
</tr>
<tr>
<td>-register_duplication</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-register_balancing</td>
<td>&nbsp;</td>
<td>No</td>
<td>NO</td>
</tr>
<tr>
<td>-optimize_primitives</td>
<td>&nbsp;</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-use_clock_enable</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-use_sync_set</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-use_sync_reset</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-iob</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-equivalent_register_removal</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-slice_utilization_ratio_maxmargin</td>
<td>&nbsp;</td>
<td>5</td>
<td>0%</td>
</tr>
</TABLE>
<A NAME="Translation Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>None</td>
</tr>
<tr>
<td>-dd</td>
<td>&nbsp;</td>
<td>_ngo</td>
<td>None</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc3s1000-ft256-5</td>
<td>None</td>
</tr>
<tr>
<td>-uc</td>
<td>&nbsp;</td>
<td>pines.ucf</td>
<td>None</td>
</tr>
</TABLE>
<A NAME="Map Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ir</td>
<td>Use RLOC Constraints</td>
<td>OFF</td>
<td>OFF</td>
</tr>
<tr>
<td>-cm</td>
<td>Optimization Strategy (Cover Mode)</td>
<td>area</td>
<td>area</td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>None</td>
</tr>
<tr>
<td>-o</td>
<td>&nbsp;</td>
<td>conversor_map.ncd</td>
<td>None</td>
</tr>
<tr>
<td>-pr</td>
<td>Pack I/O Registers/Latches into IOBs</td>
<td>off</td>
<td>off</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc3s1000-ft256-5</td>
<td>None</td>
</tr>
</TABLE>
<A NAME="Place and Route Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-t</td>
<td>&nbsp;</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>-intstyle</td>
<td>&nbsp;</td>
<td>ise</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ol</td>
<td>Place & Route Effort Level (Overall)</td>
<td>high</td>
<td>std</td>
</tr>
<tr>
<td>-w</td>
<td>&nbsp;</td>
<td>true</td>
<td>false</td>
</tr>
</TABLE>
<A NAME="Operating System Information"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Operating System Information</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td>Intel(R) Core(TM) i7-2600 CPU @ 3.40GHz/3392 MHz</td>
<td>Intel(R) Core(TM) i7-2600 CPU @ 3.40GHz/3392 MHz</td>
<td>Intel(R) Core(TM) i7-2600 CPU @ 3.40GHz/3392 MHz</td>
<td>Intel(R) Core(TM) i7-2600 CPU @ 3.40GHz/3392 MHz</td>
</tr>
<tr>
<td>Host</td>
<td>PTO0715</td>
<td>PTO0715</td>
<td>PTO0715</td>
<td>PTO0715</td>
</tr>
<tr>
<td>OS Name</td>
<td>Microsoft Windows 7 , 64-bit</td>
<td>Microsoft Windows 7 , 64-bit</td>
<td>Microsoft Windows 7 , 64-bit</td>
<td>Microsoft Windows 7 , 64-bit</td>
</tr>
<tr>
<td>OS Release</td>
<td>Service Pack 1  (build 7601)</td>
<td>Service Pack 1  (build 7601)</td>
<td>Service Pack 1  (build 7601)</td>
<td>Service Pack 1  (build 7601)</td>
</tr>
</TABLE>
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